spin_lock_irqsave(&ioapic_lock, flags);
dest = set_desc_affinity(desc, mask);
if (dest != BAD_APICID) {
- /* Only the high 8 bits are valid. */
- dest = SET_APIC_LOGICAL_ID(dest);
+ if ( !x2apic_enabled )
+ dest = SET_APIC_LOGICAL_ID(dest);
entry = irq_2_pin + irq;
for (;;) {
unsigned int data;
#define IOAPIC_EDGE 0
#define IOAPIC_LEVEL 1
+#define SET_DEST(x, y, value) \
+ do { if ( x2apic_enabled ) x = value; else y = value; } while(0)
+
static inline void ioapic_register_intr(int irq, unsigned long trigger)
{
if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
disable_8259A_irq(irq);
}
cfg = irq_cfg(irq);
- entry.dest.logical.logical_dest =
- cpu_mask_to_apicid(cfg->domain);
+ SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
+ cpu_mask_to_apicid(cfg->domain));
spin_lock_irqsave(&ioapic_lock, flags);
io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
*/
entry.dest_mode = INT_DEST_MODE;
entry.mask = 0; /* unmask IRQ now */
- entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
+ SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
+ cpu_mask_to_apicid(TARGET_CPUS));
entry.delivery_mode = INT_DELIVERY_MODE;
entry.polarity = 0;
entry.trigger = 0;
entry.dest_mode = 0; /* Physical */
entry.delivery_mode = dest_ExtINT; /* ExtInt */
entry.vector = 0;
- entry.dest.physical.physical_dest =
- get_apic_id();
+ SET_DEST(entry.dest.dest32, entry.dest.physical.physical_dest,
+ get_apic_id());
/*
* Add it to the IO-APIC irq-routing table:
entry1.dest_mode = 0; /* physical delivery */
entry1.mask = 0; /* unmask IRQ now */
- entry1.dest.physical.physical_dest = hard_smp_processor_id();
+ SET_DEST(entry1.dest.dest32, entry1.dest.physical.physical_dest,
+ hard_smp_processor_id());
entry1.delivery_mode = dest_ExtINT;
entry1.polarity = entry0.polarity;
entry1.trigger = 0;
entry.delivery_mode = INT_DELIVERY_MODE;
entry.dest_mode = INT_DEST_MODE;
- entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
+ SET_DEST(entry.dest.dest32, entry.dest.logical.logical_dest,
+ cpu_mask_to_apicid(TARGET_CPUS));
entry.trigger = edge_level;
entry.polarity = active_high_low;
entry.mask = 1;
/* Set the vector field to the real vector! */
rte.vector = cfg->vector;
- rte.dest.logical.logical_dest =
- cpu_mask_to_apicid(cfg->domain);
+ SET_DEST(rte.dest.dest32, rte.dest.logical.logical_dest,
+ cpu_mask_to_apicid(cfg->domain));
io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&rte) + 0));
io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&rte) + 1));